Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA

Abstract In sensitive communications, the cryptographic hash function plays a crucial role, including in military, healthcare, and banking, ensuring secure transmission by verifying data integrity carrying out other vital tasks. Compared to algorithms, such as SHA-1 SHA-2, Keccak (SHA-3) boasts superior hardware performance is more resilient modern cryptanalysis techniques. Nonetheless, enhancements, boosting speed or reducing area usage, are constantly required. This research focuses on increasing algorithm’s throughput rate introducing novel architecture that reduces total number of clock cycles required obtain result function. Additionally, new simplified structure round constant (RC) generator design assures reasonably low achieves highest efficiency. Thus, when implemented, it achieved 19.515 Gbps, 24.428 33.393 36.358 Gbps FPGA devices with Virtex-5, Artix-7, Virtex-6, Virtex-7, respectively. Finally, our approach compared recently published designs.